1. Field of the Invention
The present invention relates to a semiconductor fabrication, and more particularly to accurately measuring topology of a wafer, thereby allowing reduction of focusing error of an exposure process.
2. Description of Related Art
In a DRAM of interest, a lower electrode layer in the information storing capacitor of each memory cell extends vertically upwards, the difference in height between a memory cell array region( or area) and a peripheral circuit region( or area) is very large.
Scanner systems require accurately controlled-focusing and tilting so as to obtain exposure reliability to a wafer whereon a variety of structures are formed. One example of a system which controls the focusing and tilting is a capacitance gauge tracking system(hereinafter referred to "CGTS")(see FIG. 1). The CGTS tracks the capacitance between a wafer surface and a capacitance gauge to control focusing and tilting before the exposure process. Another example of system is known optical multi-point focusing system.
FIG. 1 schematically shows a CGTS 16. As illustrated, a wafer 12 is mounted over a wafer stage 10. The CGTS 16 measures the capacitance between the wafer 12 surface and a capacitance gauge 14 by moving the grounded wafer 12 or the capacitance gauge 14 according to X-Y direction. The resulting equivalent circuits in accordance with tracking of FIG. 1 are schematically illustrated in FIGS. 2A and 2B, respectively at peripheral region and cell array region. In FIGS. 2A and 2B, a reference numeral "R" represents equivalent resistance of the wafer, "C-oxide" represents capacitance of an oxide layer at the peripheral region, "R.sub.p " represents equivalent resistance of a polysilicon, "C-air" represents capacitance of an air between the wafer 12 and capacitance gauge 14, and a reference numeral "20" represents constant current source applied from CGTS 16.
From the equivalent circuits of FIGS. 2A and 2B, C-peri(capacitance of peripheral region), C-array(capacitance of cell array region), C(capacitance) are given by the following equations, ##STR1## C-array=C-air (2) EQU C=.epsilon.(A/d) (3)
where ".epsilon." is permittivity, "A" is an area, and "d" is a distance between adjacent conductors.
Permittivity of air is about 1 and permittivity of an oxide layer is about 4. From the above mentioned equations, C-air(capacitance of air) becomes A/100, and C-oxide(capacitance of oxide) becomes 4A. If the peripheral region is filled with about 1 micrometers thick oxide layer, C-peri becomes A/104 from equation 1. There should be the difference of about 4 micrometers in height between cell array region and peripheral region if the same C-peri(i.e., A/104) is obtained by using air instead of the oxide.
However, the real height difference there between is about 0.3 micrometers. Therefore, CGTS incorrectly tracks the capacitance of the wafer surface(i.e., calculated capacitance differs from the real capacitance), since capacitances of the polysilicon(cell array region) and the oxide layer(peripheral region) are different from one another. As a result, defocusing problems can arise during the exposure process.